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| TBIL2024 | Digital Design | 2+0+0 | ECTS:3 | | Year / Semester | Spring Semester | | Level of Course | Short Cycle | | Status | Elective | | Department | DEPARTMENT of COMPUTER TECHNOLOGIES | | Prerequisites and co-requisites | None | | Mode of Delivery | | | Contact Hours | 14 weeks - 2 hours of lectures per week | | Lecturer | Öğretim Görevlisi Fatih ÜÇÜNCÜ | | Co-Lecturer | | | Language of instruction | Turkish | | Professional practise ( internship ) | None | | | | The aim of the course: | | How to design and analyze sequential synchronous and asynchronous circuits, How to relate physical events to sequential or combinational circuits, Design and implementation of basic computer hardware functions |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | Gain analysis and design skills in pulse mode and level mode asynchronous circuits. | 6 | 1, | | LO - 2 : | Gain the ability to solve risk and racing problems in level mode circuits. | 6 | 1, | | LO - 3 : | Gain clocked sequential circuit analysis and design knowledge with flip-flop circuit elements. | 6 | 1, | | LO - 4 : | Gain the ability to communicate between the analog and digital world. | 6 | 1, | | LO - 5 : | Can gain theoretical skills in sequential circuit design with ROM and PLD mechanisms. | 6 | 1, | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Electrical structure of logic gates, Multiple-output logic circuits, ROM memories, Programmable mechanisms PLA-PAL; Flip-flops; Counters and similar sequential circuits; Analysis of clocked sequential circuits; Obtaining status graphs and tables; Reduction of state assignments in the state table; MSI integrated circuits in sequential circuit design; Design of sequential circuits using Programmable Logic Mechanisms and ROM. State mechanism design with SM cards; Analysis and design of pulse mode asynchronous circuits; Analysis of level-mode asynchronous sequential circuits, Primitive flow table extraction and reduction in level-mode circuits; Implementation of flow tables with state assignments, Risks in level mode circuits; Asynchronous circuit design, Interface between analog and digital media. |
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Discrete and integrated logic circuit design
| | | Week 2 | Flip-Flops, Counters and similar sequential circuits | | | Week 3 | Analysis of clocked sequential circuits
| | | Week 4 | Extraction of status graphs and tables
| | | Week 5 | Reductions in assignments of state tables | | | Week 6 | Sequential circuit design with MSI integrated circuits
| | | Week 7 | Sequential circuit design with programmable logic mechanisms
| | | Week 8 | State machine design with SM charts | | | Week 9 | Mid-term exam | | | Week 10 | Pulse mode sequential circuit analysis and synthesis
| | | Week 11 | Level mode asynchronous sequential circuit analysis
| | | Week 12 | Inference and reduction of primitive flow tables
| | | Week 13 | Implementation of flow tables with state assignments
| | | Week 14 | Risks
| | | Week 15 | Interface with the analog world | | | Week 16 | Final exam
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| 1 | Mano, M.M.1994; Sayısal Tasarım, MEB yayınları, Ankara | | | |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Mid-term exam | 8 | | 1 | 50 | | End-of-term exam | 16 | | 1 | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | Yüz yüze eğitim | 2 | 14 | 28 | | Sınıf dışı çalışma | 1 | 14 | 14 | | Arasınav için hazırlık | 1 | 8 | 8 | | Arasınav | 1 | 1 | 1 | | Ödev | 2 | 10 | 20 | | Dönem sonu sınavı için hazırlık | 1.5 | 6 | 9 | | Dönem sonu sınavı | 1 | 1 | 1 | | Diğer 1 | 1 | 1 | 1 | | Total work load | | | 82 |
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