|
|
| EEE1006 | Digital Design | 3+0+1 | ECTS:5 | | Year / Semester | Spring Semester | | Level of Course | First Cycle | | Status | Compulsory | | Department | DEPARTMENT of ELECTRICAL and ELECTRONICS ENGINEERING | | Prerequisites and co-requisites | DC must have been achieved from EEE1001-Introduction To Computers or DC must have been achieved from EEE1009-Introduction To Computers | | Mode of Delivery | Face to face, Lab work | | Contact Hours | 14 weeks - 3 hours of lectures and 1 hour of laboratory per week | | Lecturer | Prof. Dr. Önder AYDEMİR | | Co-Lecturer | | | Language of instruction | | | Professional practise ( internship ) | None | | | | The aim of the course: | |
Understand what's under the hood of a computer.
Learn the principles of digital design.
Learn to systematically debug increasingly complex designs. |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Number systems, decimal numbers, binary numbers, powers of two, number conversions, hexadecimal numbers, bit, byte, nibble,.Adding binary numbers, signed binary numbers, complement of two. Logic gates, logic levels, noise. Logic gates familiy (TTL, CMOS, LVTTL, LVCMOS). Boolean equations, product of sums (POS), sum of products (SOP). Boolean algebra, boolean axioms, Simplifying boolean equations. DeMorgan theorem. Rules for circuit schematics. Multiple output circuits. Priority circuits Dont cares. Tristate buses. Karnough maps. Multiplexers and decoders. Types of delay. Critical paths. Glitch. Introduction to sequential circuits. Bistable circuit, SR, D latch and D flip-flop. Enabled flip flops. Resettable flip-flops. Settable flip-flops. Sequential logic. Synchronous sequential logic design.. Finite state machines (FSM). Moore vs Mealy FSM. Timing, input and output timing constraints. Setup and hold timing constraints. Timing analysis. Clock skew. Meta stablity. Synchronisers. Spatial and temporal paralellism. Hardware description languagesi (HDL). Simulation and synthesis. Systemverilog, HDL simulation. Design of adder, subtracter, comparator and ALU. Shifter, multiplier, divider. Fixed point and signed fixed point numbers. Floating point numbers. Counters, shift registers, arrays of memory, ROM, RAM, DRAM, SRAM. Designing circuits using memory. PLA and FPGA.
|
| |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | | | | | | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | | | | |
|