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| BIL2018 | Digital Design Lab. | 1+0+1 | ECTS:2 | | Year / Semester | Spring Semester | | Level of Course | First Cycle | | Status | Compulsory | | Department | DEPARTMENT of COMPUTER ENGINEERING | | Prerequisites and co-requisites | None | | Mode of Delivery | Group study, Lab work | | Contact Hours | 14 weeks - 1 hour of lectures and 1 hour of laboratory per week | | Lecturer | Dr. Öğr. Üyesi Bahar HATİPOĞLU YILMAZ | | Co-Lecturer | Other academic staff | | Language of instruction | Turkish | | Professional practise ( internship ) | None | | | | The aim of the course: | | To have practical learning with set up the logic and electronic devices, to compare theories of the lectures information with practical devices. |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | gain practices for logical circuits by using lojgic chips and practical experiments | 1.1 - 1.3 - 2.2 - 5.3 | 1,4 | | LO - 2 : | have practical learning with set up the logic and electronic devices | 1.1 - 1.3 - 2.2 - 5.3 | 1,2 | | LO - 3 : | compare theoris of the lectures information with practical devices. | 1.1 - 1.2 - 1.3 - 2.2 - 5.3 | 2,4 | | LO - 4 : | make practical experiments for synchronous and asynchronous network design and analysis, | 1.1 - 1.3 - 2.2 - 5.3 | 1,2,4 | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Multivirators, Coding and error sstimation Techniques, Boole functions, Counters, Level-mode sequential networks, Pulse-mode sequential networks, Hazards and Risks in the logic circuits and their elimination, Edge triggered D Flip-Flop, Sequential network design with ROMs and PLDs, Design sequential network with MSI Integrated circuits. |
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Making students groups in Lab. | | | Week 2 | Lab advertisement for lab experiments | | | Week 3 | Multivirators, | | | Week 4 | Coding and error sstimation techniques | | | Week 5 | Boole functions | | | Week 6 | Counters | | | Week 7 | Level-mode sequential networks | | | Week 8 | Mid-term exam | | | Week 9 | Pulse-mode sequential networks | | | Week 10 | Hazards in the logic circuits and their elimination | | | Week 11 | Edge triggered D Flip-Flop | | | Week 12 | Sequential network design with ROMs and PLDs, | | | Week 13 | Design sequential network with MSI Integrated circuits | | | Week 14 | Compensation Experiments | | | Week 15 | Practice of an experimental design | | | Week 16 | End-of-term exam | | | |
| 1 | Lecture Notes for for Lab experiments | | | |
| 1 | Roth, Charles H. , 1992, Fundamentals of Logic Design, Fourth Edition, West Publishing Company | | | |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Laboratory exam | 3
4
5
6
7
9
10
11
12
13 | 18/02/2014 | 2 | 30 | | Practice | 15 | 21/05/2014 | 2 | 20 | | End-of-term exam | 16 | 28/05/2014 | 2 | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | | | | |
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