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| BIL3017 | Hardware Description Languages | 3+0+0 | ECTS:4 | | Year / Semester | Fall Semester | | Level of Course | First Cycle | | Status | Elective | | Department | DEPARTMENT of COMPUTER ENGINEERING | | Prerequisites and co-requisites | None | | Mode of Delivery | Face to face, Group study | | Contact Hours | 14 weeks - 3 hours of lectures per week | | Lecturer | Dr. Öğr. Üyesi Şeyma AYMAZ | | Co-Lecturer | | | Language of instruction | Turkish | | Professional practise ( internship ) | None | | | | The aim of the course: | | The objectives of course are (a) to cover basics of a hardware description language (VHDL) (b) to obtain the ability of designing Finite State Machines (FSMs) (c) to learn how to design basic hardware modules such as register, counter and etc. (d) to use an FPGA board. |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | Learn embedded systems basics | 1.3 - 2.1 - 4.1 | | | LO - 2 : | Learn a hardware description laguage (HDL) | 1.3 - 2.1 - 3.1 - 4.1 | | | LO - 3 : | Design and develope hardware modules with the HDL | 1.3 - 2.1 - 2.2 - 3.1 | | | LO - 4 : | Perform computer based simulation and applies to real hardware | 1.3 - 2.1 - 3.1 - 4.1 | | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Embedded design concepts. Basic structure of a hardware description language. Designing and implementing combinational and sequential circuits in VHDL hardware description language. |
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Introduction
| | | Week 2 | Course Introduction, Historical Perspective, Digital Products, and Their Impact on Modern Life
| | | Week 3 | Introduction to VHDL Hardware Description Language
| | | Week 4 | Design of Combinational Circuits in VHDL Hardware Description Language
| | | Week 5 | Design of 1-Bit and 4-Bit Adder Circuits in Hardware Description Language
| | | Week 6 | Testing of Circuits Designed in VHDL | | | Week 7 | Design of Sequential Circuits in Hardware Description Language
| | | Week 8 | Design of Counters in Hardware Description Language | | | Week 9 | Midterm exam
| | | Week 10 | Finite State Machines (FSM) in VHDL
| | | Week 11 | Design of Moore and Mealy Type Finite State Machines
| | | Week 12 | Component Creation in VHDL
| | | Week 13 | Using the Input/Output Modules of the Xilinx Spartan Starter Kit
| | | Week 14 | Testing the Adder Circuit with the Spartan Starter Kit | | | Week 15 | Testing the Counter Module with the Training Unit | | | Week 16 | Final Exam | | | |
| 1 | Zwolinski, Mark, Digital system design with VHDL, Prentice Hall, 2003: 2nd ed. | | | |
| 1 | Perry, Douglas L. , VHDL: programming by example, McGraw-Hill, 2002 : 4th ed. | | | |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Mid-term exam | 9 | | 2 | 30 | | Project | 14 | | 2 | 20 | | End-of-term exam | 16 | | 2 | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | Yüz yüze eğitim | 3 | 14 | 42 | | Sınıf dışı çalışma | 2 | 9 | 18 | | Arasınav | 2 | 1 | 2 | | Uygulama | 1 | 3 | 3 | | Proje | 2 | 12 | 24 | | Dönem sonu sınavı | 2 | 14 | 28 | | Total work load | | | 117 |
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